1. Technical Field
The present invention relates to a multiprocessor system, and particularly to a technique for sharing data among processors.
2. Background Art
As a method for sharing data among a plurality of processors in a multiprocessor system, the following method (so-called tightly-coupled multiprocessor system) is known. Data to be shared is stored in a single shared memory, and processors access this shared memory so as to share the data with one another.
This method has an advantage that the identity of shared data used by processors can be easily maintained. On the other hand, this method is problematic in that, as processors increase in number, they are more likely to contend with one another for accessing the shared memory, which results in lowering of the processing efficiency of the entire system.
This is particularly problematic in processes that require real-time performance, such as a process to receive digital broadcasting data, e.g. image data, transmitted from a broadcast station, and to decode the data for display.
As a means for solving this problem, the following method (so-called loosely-coupled multiprocessor system) is known. Each processor has a dedicated memory for storing therein a copy of shared data, and each accesses its own dedicated memory. (e.g. Patent Documents 1 and 2).
FIG. 30 shows a conventional data-sharing method used in the loosely-coupled multiprocessor system.
As shown in FIG. 30, a dedicated memory 3A is used by a processor 1A, a dedicated memory 3B by a processor 1B, and a dedicated memory 3C by a processor 1C. Each dedicated memory has a predetermined shared area for storing therein a copy of shared data.
When an access request is transmitted from each processor to access its dedicated memory, a memory control device 4 controls bus selection circuits 5A-5C according to whether the access request is to write data in the shared area in the dedicated memory.
For example, when an access request from the processor 1A is a write request to write data in its shared area, the memory control device 4 controls the bus selection circuits 5A-5C to write the data in the shared areas of the dedicated memories 3A-3C. When the access request from the processor 1A is a request to write data in other area than its shared area or to read out data from either of the areas, the memory control device 4 controls the bus selection circuits 5A-5C to access solely the dedicated memory 3A.
As a result, when the shared data in the dedicated memory of one of the processors is updated, the shared data in the dedicated memory of each of the remaining processors is also updated. Therefore, the identity of the shared data can be maintained. In addition, it is only when a write request is made to write data in the shared area in the dedicated memory of one of the processors, the shared data in the dedicated memory of each of the remaining processors is updated. This reduces the possibility of occurrence of access contention.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 61-122771
Patent Document 2: Japanese Unexamined Patent Application Publication No. 3-127248